Commits · master · Christian Jair Luis Pena / Learn Fpga

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May 23, 2023
- Added new peripherals · af66c2f7
  Christian Jair Luis Pena authored May 23, 2023
  
  af66c2f7
- Adding ICEBREAKER peripherals · d2eccab1
  Christian Jair Luis Pena authored May 23, 2023
  
  d2eccab1
Apr 05, 2023
- Updated toolchain installation instruction: using precompiled packages · a5e79949
  Bruno Levy authored Apr 5, 2023
  a5e79949
Jan 08, 2023
- Systematically initialize registers to zero (and not only in BENCH mode) · 408c2441
  Bruno Levy authored Jan 8, 2023
  
  408c2441
- Still testing what happens in VIVADO: included display of current · aabd49bd
  Bruno Levy authored Jan 8, 2023
  aabd49bd
- Fixes for VIVADO · ecaf593c
  Bruno Levy authored Jan 8, 2023
  
  ecaf593c
- * added step7 with disassembler for testing what happens with Vivado (issue #87) · 253a2df5
  Bruno Levy authored Jan 8, 2023
  253a2df5
Nov 24, 2022
- New script to install YOSYS/NEXTPNR for ICE40-based FPGAs · 1ccf098e
  Bruno Levy authored Nov 24, 2022
  
  1ccf098e
Oct 12, 2022
- * Added precompiled RAYSTONES, DHRYSONES and COREMARK · 0a97ede5
  Bruno Levy authored Oct 12, 2022
  0a97ede5
Oct 02, 2022
- * Added new frequencies in PLL (now we got something that runs · cecdaf7a
  Bruno Levy authored Oct 2, 2022
  cecdaf7a
Sep 26, 2022
- typos. · dd7b10b4
  Bruno Levy authored Sep 26, 2022
  
  dd7b10b4
Sep 25, 2022
- Added step on RV32M · 7ae0d320
  Bruno Levy authored Sep 25, 2022
  
  7ae0d320
- typo ! · 55a61df8
  Bruno Levy authored Sep 25, 2022
  
  55a61df8
- Small fixes in step 9 · c802104a
  Bruno Levy authored Sep 25, 2022
  
  c802104a
- BRAM, not DRAM ! · 5e492572
  Bruno Levy authored Sep 25, 2022
  
  5e492572
- Finished writing tutorial for step 9 (RAS) · 2ef4bf4e
  Bruno Levy authored Sep 25, 2022
  
  2ef4bf4e
Sep 19, 2022
- Restored % 21 instead of & 15 (now we have div/rem in pipelineY.v) · a750d573
  Bruno Levy authored Sep 19, 2022
  
  a750d573
- better "progress bar"... · 0bbee839
  Bruno Levy authored Sep 19, 2022
  
  0bbee839
- * added missing .section DATA in assembly programs · 587f5a75
  Bruno Levy authored Sep 19, 2022
  587f5a75
Sep 18, 2022
- cCleanup, comments. · 9e08dcec
  Bruno Levy authored Sep 18, 2022
  
  9e08dcec
- Ooops, `ifdef RV32M instead of CONFIG_RV32M broke everything !!! · e6ad7e38
  Bruno Levy authored Sep 18, 2022
  
  e6ad7e38
- Comments · f252a968
  Bruno Levy authored Sep 18, 2022
  
  f252a968
- Made RV32M optional · e98c91ae
  Bruno Levy authored Sep 18, 2022
  
  e98c91ae
- Replaced several imbrications of muxes with big "or" expression in · dafd0f92
  Bruno Levy authored Sep 18, 2022
  dafd0f92
- Added comments. · 631db7b0
  Bruno Levy authored Sep 18, 2022
  
  631db7b0
- cleaner division. · 42c2ebbb
  Bruno Levy authored Sep 18, 2022
  
  42c2ebbb
- cleaner divide, without divResult reg (now uses mux on · 837c5eef
  Bruno Levy authored Sep 18, 2022
  837c5eef
- - Removed registered branch prediction (does not gain anything) · 5d211287
  Bruno Levy authored Sep 18, 2022
  5d211287
- 300 iterations (else not enough to measure timings) · e82bc09c
  Bruno Levy authored Sep 18, 2022
  
  e82bc09c
- Fixed load-after-store bug by inserting a bubble : · 503b0b79
  Bruno Levy authored Sep 18, 2022
  503b0b79
- Found bug in pipelineX and pipelineY: when storing at an address and · 9bd5b94c
  Bruno Levy authored Sep 18, 2022
  9bd5b94c
Sep 17, 2022
- - Added reg fwd display in debug. · 3f4ee1fb
  Bruno Levy authored Sep 17, 2022
  3f4ee1fb
Sep 16, 2022
- pipelineY: added MUL instructions · e63efbcf
  Bruno Levy authored Sep 16, 2022
  e63efbcf
- Added "debugger" · 68261c87
  Bruno Levy authored Sep 16, 2022
  
  68261c87
- Comment. · 261d75ff
  Bruno Levy authored Sep 16, 2022
  
  261d75ff
- Fixed computation of load hazard statistics · 0d49dee7
  Bruno Levy authored Sep 16, 2022
  0d49dee7
- Added statistic in bench mode. · 2e9f7027
  Bruno Levy authored Sep 16, 2022
  
  2e9f7027
- * riscv_disassembly.v: added utility functions in riscv_disasm (RV32I... · 69244a83
  Bruno Levy authored Sep 16, 2022
  69244a83
- Added generic version of optimized pipelined CPU. · 91e5a4ef
  Bruno Levy authored Sep 16, 2022
  
  91e5a4ef
Sep 14, 2022
- More optimizations in D stage, and registered D_predictBranch. · 1d4df167
  Bruno Levy authored Sep 14, 2022
  
  1d4df167